This invention relates generally to testing schemes for microelectronic memories, and more particularly, to a self-testing memory system for a dynamic RAM, the system using circuitry included on the memory chip for testing all common failure modes.
The testing of computer memories has always been difficult and time consuming, and more recently, as microelectronic memories become available in increased capacities, illustratively into the 1 Megabit range, significant problems are encountered in reliably and economically testing such memory for each of the large variety of the possible failure modes. Improvements in very large scale integration (VLSI) technology have resulted in dramatic increases in the capacities of random access memories (RAMs), particularly dynamic integrated RAMs. Under some widely used existing test schemes, the testing time is proportional to the square of the capacity of the memory. Thus, the testing of a 1K RAM may take only a few seconds, but the testing of a 64K RAM may require several hours. In addition, as memory size increases, additional and complex failure modes, such as pattern sensitivity, become more common. Testing for such complex failure modes rapidly increases the test complexity.
GALPAT is a widely used test procedure which is of the type requiring test time to be proportional to the square of the memory capacity. This known testing procedure is heuristic in nature, thereby providing incomplete fault coverage. In essence, the GALPAT procedure requires writing a zero value into each of the storage cells of the RAM. A one value is then written into the first cell, and the remaining cells are read and their contents are verified in turn. After each such cell is checked to see that it correctly stores a zero value, the first cell, in which the one value is stored, is checked to insure that its data has not been changed by failure-induced interaction between cells. This testing step requires 2n read operations and is repeated with each cell serving sequentially as the test cell. The entire process is then repeated with the zero values and one values interchanged. There are therefore required approximately 4n.sup.2 read and write operations to execute the GALPAT procedure.
Prior art efforts at reducing testing time of a digital system have resulted in the production of self-testing RAMs by use of known error detecting and error correcting codes. It is a problem with such error detecting systems that substantial extra circuitry is required to generate and store various signals and check bits. Such systems may also require extensive replication for purpose of comparison which also increases circuit complexity and cost. In addition to such complexity and cost, error detecting systems using codes suffer from the further disadvantage that fault coverage is difficult to determine. Moreover, the complete replication of a design for purposes of massive redundancy on a single chip is too costly for most applications. Thus, known systems for testing RAM designs using coding or replication techniques rely on external sources to provide the various test sequences required to achieve complete testing of a chip, and accordingly, little work has been done to achieve on-chip test generation. Notwithstanding such use of complex external testing apparatus, many types of physical faults cannot be detected by any given error-detecting code.
It is therefore, an object of this invention to provide a testing system for dynamic RAMs which achieves testing in a relatively short period of time.
It is another object of this invention to provide a memory test system applicable to a variety of memory capacities wherein the test time is not necessarily related to the square of the memory capacity.
It is also an object of this invention to provide a memory test system which does not require massive redundancy to achieve testing.
It is an additional object of this invention to provide a test scheme which is not heuristic.
It is a further object of this invention to provide a test scheme which is suitable for RAMs.
It is additionally an object of this invention to provide a memory test system which is installed on RAM chips themselves.
It is still another object of this invention to provide a memory test system which tests a plurality of storage cells simultaneously.
It is a yet further object of this invention to provide a memory test system which can detect a variety of failure modes in addition to single cell defects.
It is also another object of this invention to provide a memory test system which can self-test a computer memory system.
It is still an additional object of this invention to provide a memory test system which can restructure a memory system using excess storage cells to correct for detected defects.
It is also a further object of this invention to provide a memory test system which can be installed on a memory chip without extensive modification of conventional circuitry already on the memory chip.
It is yet an additional object of this invention to provide a memory test system which uses memory control and logic circuitry already on the memory chip in performance of the testing function.
It is a still further object of this invention to provide a memory test system which uses memory refresh circuitry of the type which is installed in known memory chips.
It is also an additional object of this invention to provide a memory test system which can be applied to a variety of known RAM chip organizations without significant changes to the system.
It is yet another object of this invention to provide a memory test system which can detect defects in dynamic MOS memories resulting from gate oxide defects.
Another object of this invention is to provide a memory test system which can detect defects in dynamic MOS memories resulting from leakage from a storage cell capacitor.
A further object of this invention is to provide a memory test system which can detect defects in dynamic MOS memories resulting from leakage from a bit line.
An additional object of this invention is to provide a memory test system which can detect defects in dynamic MOS memories resulting from parasitic resistance.
A yet further object of this invention is to provide a memory test system which can detect defects in dynamic MOS memories resulting from parasitic capacitance.
Yet an additional object of this invention is to provide a memory test system which can detect failure modes in address buffers.
A still further object of this invention is to provide a memory test system which can detect failure modes in address decoders.
Additionally, it is an object of this invention to provide a memory test system which can detect failure modes in refresh control logic circuitry.
A yet further object of this invention is to provide a memory test system which can detect failure modes in data buffers.